EVENT_CNT_2=Val_0x0, EVENT_CNT_0=Val_0x0, CYCLE_CNT=Val_0x0, EVENT_CNT_3=Val_0x0, EVENT_CNT_1=Val_0x0
Performance Monitor Count Enable Clear Register
| EVENT_CNT_0 | Disable PMU event counter 0. 0 (Val_0x0): When read, it means the event counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter is enabled. When written, it disables the event counter. |
| EVENT_CNT_1 | Disable PMU event counter 1. 0 (Val_0x0): When read, it means the event counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter is enabled. When written, it disables the event counter. |
| EVENT_CNT_2 | Disable PMU event counter 2. 0 (Val_0x0): When read, it means the event counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter is enabled. When written, it disables the event counter. |
| EVENT_CNT_3 | Disable PMU event counter 3. 0 (Val_0x0): When read, it means the event counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the event counter is enabled. When written, it disables the event counter. |
| CYCLE_CNT | Disable PMU cycle counter. 0 (Val_0x0): When read, it means the cycle counter is disabled. When written, it has no effect. 1 (Val_0x1): When read, it means the cycle counter is enabled. When written, it disables the cycle counter. |